The functions included in a Lane Module depend on:
- The type of lane (Clock, Unidirectional Data, or Bi-directional Data)
- The side of the Lane Interconnect (Master or Slave)
There are three main Lane types:
- Clock Lane
- Unidirectional Data Lane
- Bi-directional Data Lane
Different PHY Configurations are created by combining these Lane types.
A Universal Lane Module architecture exists that can be adapted to any Lane type, with internal functionality controlled by the Control and Interface Logic (CIL) block.
Universal Lane Module
- The Control & Interface Logic (CIL) determines which functions are active.
- The exact CIL implementation depends on:
- Lane type (Clock / Uni-directional / Bi-directional)
- Lane side (Master / Slave)
- The specification defines behavior; implementation details are flexible.
Stripped-Down Lane Modules
To simplify implementations, versions of the Universal Lane Module may include only the required features.
These reduced versions are described using CIL-type acronyms (see Table 1).
You may replace any letter with X meaning “don’t care / any allowed option”.
Examples:
| Example | Meaning |
|---|---|
| CIL-MFEN | Master side, Unidirectional Lane, Escape Mode only in Forward direction |
| CIL-SRXX | Slave side, Bi-directional Lane supporting High-Speed Reverse, with any Escape Mode options |
Link Direction Implications
- A designation CIL-XFXN implies a Unidirectional Link.
- A designation CIL-XRXX or CIL-XXXY implies a Bi-directional Link.
- Escape entry signaling differs between Clock and Data lanes.
Table 1 — Lane Type Descriptors
| Segment | Meaning / Options |
|---|---|
Prefix CIL- |
Control & Interface Logic block |
| Lane Interconnect Side | M = Master, S = Slave, X = Don’t care |
| High-Speed Capabilities | F = Forward-only, R = Forward + Reverse, X = Don’t care (Data Lanes only) |
| Forward Escape Mode Features | A = All (includes LPDT), E = Triggers + ULPS only, X = Don’t care |
| Reverse Escape Mode Features | A = All (includes LPDT), E = Triggers + ULPS only, N = None, Y = Any allowed combination, X = Don’t care |
| Clock Lanes | Always use C for Lane type; Escape Mode does not apply |
Note:
- “Any” means one or more of the listed capabilities.
- High-speed F/R selection (
ForR) only applies to Data Lanes.
PHY Protocol Interface (PPI)
A recommended PPI includes:
- Data-in and Data-out (byte format)
- Clock signals (input or output depending on Master/Slave)
- Control signals, such as:
- Requests
- Handshakes
- Test configuration
- Initialization signals
For external chip interfaces, implementations may multiplex signals to reduce pin count.
However, within the IC, separate PPI signals are usually kept for power efficiency.